The invention relates to the field of printed circuit board (PCB) design. More specifically, the invention relates to designing PCBs using a method and system that accepts both textual and graphical inputs.
Currently there are two common design entry techniques for accomplishing PCB design: text based such as Very High Speed Integrated Circuits Hardware Description Language VHDL) Verilog and manual graphic-based schematic entry. In the proceeding text, VHDL will be used to refer to both VHDL and Verilog text-based design entry. Both techniques (text and graphic) offer distinct advantages, and present corresponding inherent disadvantages. For example, VHDL aids a designer by allowing simulation of the PCB prior to manufacture, while schematic entry allows the designer to design both logic and non-logic PCB components. To date, however, there is no single PCB design process that captures both VHDL and schematic entry data. As a result, designers often are restricted to using either VHDL or schematic entry, or adopting two independent and redundant design processes for the same circuit board (i.e., one for VHDL and the other for schematic entry). This limitation prevents the PCB designer from using the benefits of VHDL and schematic entry to design the same board, for example. In many applications, the ability to use such a combination of techniques for one board would provide a faster and more efficient PCB design process.
FIG. 1 is a flowchart showing one example of a prior art PCB design method 100. Significantly, design method 100 comprises two independent methods: VHDL entry beginning at step 103, and graphical schematic entry beginning at step 109. First, for the VHDL entry method, in step 103, the designer creates VHDL only for the logic design elements of the PCB. In step 104, the designer enters the VHDL into a semi-automated VHDL interconnect program. The semi-automated VHDL interconnect program outputs an HDL Netlist, in step 105. Those skilled in the art will appreciate that, generally speaking, a Netlist comprises a list of physical circuit components, along with the interconnections between those components. Thus, a Netlist defines the interconnections between all functional elements in a physical circuit. By simulating the operation of the physical circuit represented by the Netlist, the proper operation of the entire physical circuit can be verified prior to fabrication of the PCB.
In step 106, the designer manually enters any non-automated interconnections. In step 107, both non-automated interconnections and the HDL Netlist (which includes the automated connections) are run through a simulation program. In step 108, the output of the simulation program is reviewed by the designer to decide whether the simulation is satisfactory. If the designer is not satisfied with the simulation output, the VHDL may be revised and recreated and returned to step 103 to begin the process anew. If, on the other hand, the designer is satisfied with the simulation output, the designer may determine whether to create a graphical schematic, in step 111. In step 109, the graphical schematic is created manually from the knowledge gained from the VHDL entry process. The line between steps 109 and 111 is shown dashed because the designer can not use the output of the simulation program from step 107 to automatically create schematics in step 109. Instead, the designer simply takes the confidence and experience gained through the VHDL entry method beginning at step 103, and creates a graphical schematic entry in step 109. If the designer does not wish to create a schematic version of VHDL entry, the PCB may be manufactured in step 112.
Alternatively, the designer may begin PCB design method 100 at step 109. In this instance, the designer first manually creates graphical schematics that include both logic and non-logic PCB components. As discussed, these graphical schematics may be either the first step in the design process (at step 109), or may follow the VHDL entry method (after step 111 as described above). In either case, the designer creates the schematic entry anew. In step 110, the graphical schematic entry is entered into design software, for example PCB design software, commercially available as DESIGN ARCHITECT from MENTOR GRAPHICS. The designer may then use the output of PCB design software to manufacture the PCB, in step 113.
There are many disadvantages associated with prior art method 100. For one, with the schematic entry method (beginning at step 109), logic and non-logic portions of the PCB design are entered into the design software, in step 110, without undergoing simulation. A second disadvantage results from the inability to translate automatically the logic portions of the VHDL entry method (beginning at step 103) into the schematic entry method (beginning at step 109). A third disadvantage is that simulation step 107 in the VHDL entry method permits designers to become inattentive to programming efficiency concerns. In other words, designers who use schematic entry method (i.e., begin at step 109) tend to produce more efficient designs than those who use VHDL entry method (i.e., begin at step 103), because of simulation step 107. There are, on the other hand, certain advantages associated with prior art method 100. For one, the simplicity of prior art method 100 permits easier adaptation to changes in design requirements, simulation software, and PCB design software.
FIG. 2 is a flowchart showing a second example of a prior art PCB design method 200. Significantly, and unlike prior art PCB design method 100 as discussed with reference to FIG. 1, design method 200 allows VHDL entry of both logic and non-logic design elements, in step 201. After the designer creates VHDL for logic and non-logic design elements in step 201, the VHDL is entered into a semi-automated interconnect program in step 202. In step 203, the interconnect program creates a HDL Netlist, while the VHDL simultaneously is loaded into a file-mapping software in step 212. The file-mapping software is a physical to logical map file program that converts the interconnected VHDL into, for example, a MENTOR GRAPHICS-specific file format, for later use in step 207.
HDL Netlist obtained from step 203 is entered into a simulation program in step 204. However, because only the logic element portions of HDL Netlist can be simulated, the designer must hide (i.e., xe2x80x9cremxe2x80x9d) the non-logic portions from the simulator. However, the non-logic portions can not be completely removed from the Netlist because they are relevant for later use in design method 200. In step 205, the designer decides whether the simulation is satisfactory. If the designer is not satisfied with the results of simulation program from step 204, the VHDL may be revised, recreated and returned to step 201 to begin the process anew. If, on the other hand, the designer is satisfied with the results of simulation program 204, the program is entered into a translator software program, for example, SYNOPSYS INTERFACE FILE FORMAT (SIFF) software, available from SYNOPSYS, Incorporated.
In step 207, the translator software converts the VHDL into a format acceptable to the PCB design software, for example MENTOR GRAPHICS software. At this point, in step 208, the designer reviews the output of the PCB design software to determine if the output is satisfactory. If the designer is not satisfied with the results of the PCB design software in step 208, the program may be returned to step 206 and reentered in the translator software. If, on the other hand, the designer is satisfied with the results of the PCB design software, the designer determines whether improved, more xe2x80x9creadablexe2x80x9d schematics are desired in step 209. If improved schematics are desired, the designer undergoes a manually intensive effort in step 210 to provide more xe2x80x9creadablexe2x80x9d schematics. If, on the other hand, improved schematics are not desired the designer may use the output of the PCB design software to manufacture the PCB, in step 211.
As with prior art method 100 discussed with reference to FIG. 1, there are many disadvantages associated with prior art method 200. For one, although prior art method 200 captures non-logic design concerns as well as logic concerns, it is more complicated than prior method 100. Yet, the non-logic portion must be hidden manually (e.g., xe2x80x9crem-edxe2x80x9d) before the design can be entered into the simulator program, in step 204. Therefore, simulation is more complicated and time-consuming. In addition, in comparison to prior art method 100, prior art method 200 requires an additional step before entering the PCB design software. In particular, the logic portion of the VHDL and the logic and non-logic portions of the schematic entry must be passed through the translator software. Finally, the overall additional complexity of prior art method 200 makes it more resistant to the inevitable design and software changes that arise. Moreover, because prior art method 200 relies on independent commercially-available software products (e.g., SIFF, simulation software, and file mapping software), any software change to one product often requires the difficult coordination of numerous other products made by different vendors.
Therefore, there is a need to permit designers to utilize both VHDL entry and schematic entry techniques in the creation of one PCB without the unnecessary redundancy found in existing design methods.
In view of the above-mentioned limitations in the prior art, the invention provides a method, system, and computer-readable medium having computer-executable instructions for designing a PCB using both HDL design elements and schematic design elements, and for designing, simulating and formally verifying a PCB using both VHDL and schematic entry techniques. In particular, the inventive method comprises the steps of selecting the HDL design elements and selecting the schematic design elements. The inventive method further comprises automatically interconnecting the HDL design elements, and automatically interconnecting the schematic design elements. The PCB is then physically designed based on the interconnected HDL and schematic design elements. The method may further comprise creating a schematic version from the interconnected HDL design elements, and creating a HDL version from the interconnected schematic design elements. The inventive method also may simulate the schematic version of the HDL design elements, and simulate the HDL version of the schematic design elements. In either case, the non-logic portions of the HDL version and the schematic version may be automatically removed prior to simulating.
A system for designing a PCB using HDL design elements and schematic design elements. The system includes a HDL interconnect component for automatically interconnecting inputted VHDL logic design elements, and a simulation component in communication with the HDL interconnect component. The simulation component simulates the VHDL logic design elements. The inventive system further includes a design capture component in communication with the HDL interconnect component and the simulation component. The design capture component receives logical and non-logical graphical device inputs. Also, the system includes a physical design component in communication with the design capture component. The physical design component designs electrical paths between the logical graphical device inputs. The inventive system further may include a HDL logic import component in communication with the HDL interconnect component and the simulation component, and an interface component in communication with the HDL logic import component and the design capture component. The interface component and the HDL logic import component convert the inputted VHDL to a form compatible with the design capture component. The system also may include a HDL logic export component in communication with the design capture component and the HDL interconnect component. The HDL logic export component converts the VHDL to a form compatible with the simulation environment.